6 research outputs found

    The Impact of Capital Structure on Firm’s Performance ( A case of Non-Financial Sector of Pakistan)

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    This paper tends to investigate the impact of capital structure on the firm performance of the firms from the non-financial sector of Pakistan. Non-financial firms listed on Karachi Stock Exchange are taken as the sample size for the study. For measuring the performance of the firms Return on Assets (ROA), Return on Equity (ROE), Net Profit Margin (NPM) and Earning per Share (EPS) are used as proxies. Short Term Debt (STD), Long Term Debt (LTD) and Leverage of the Firm or Total Debt (LEV) are variables for the capital structure. Controlled variables installed in the study are Size of the Firms (SIZE), Sales Growth (SALG), Assets Growth (ASSG) and Assets Turnover or Efficiency of the Firm (ASST). The total firms were 441, due to incomplete data it came down to 380 firms. Ordinary Least Square (OLS) method is used to analyze the performance, data is taken from 2005 to 2011 i.e. 7 years. Short Term Debt (STD), Long Term Debt (LTD) and Leverage of the Firm (LEV) have a negatively affected Return on Assets (ROA). Return on Equity (ROE) has a negative relation with all the capital structure variables but with Long Term Debt (LTD) and Leverage of the Firm (LEV) it was insignificant. In case of Net Profit Margin (NPM) the impact was positive but was insignificant for all the variables i.e. Long Term Debt (LTD), Short Term Debt (STD) and Leverage of the Firm (LEV). All the capital structure variables negatively affected Earning per Share (EPS) and were significant. Assets Turnover affected the performance positively for all proxies except Net Profit Margin (NPM) for which it was positive but insignificant. Size of the firm positively affected the performance overall while Sales Growth (SALG) has a significantly negative impact on Return on Assets. Assets Growth was found to have on impact on the performance of the firms. Keywords: Capital Structure, Firm’s Performanc

    Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication

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    Power, performance and reliability optimisation of on-chip interconnect by adroit use of dark silicon

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    Continuous transistor scaling has enabled computer architecture to integrate increasing numbers of cores on a chip. Packet switched Network-on-Chip (NoC) is envisioned as a scalable and cost effective communication fabric for multicore architectures with tens and hundreds of cores. Extreme transistor scaling (45nm and beyond) has its own share of technical challenges. For recent technology nodes, the power per transistor is not reducing at the same rate as area. Failed Dennard's Scaling has resulted in a situation where we have abundant transistors, but not enough power to switch on these transistors at the same time, a phenomenon termed Dark Silicon. Previous research on dark silicon concentrated on integrating application specific accelerators or cores to improve energy efficiency and reliability, completely neglecting the interplay of dark silicon and NoC architecture.For the first time, this thesis proposes various NoC architectures that exploit dark silicon to improve the energy efficiency, performance and reliability of the on-chip interconnect. The first proposal is an on-chip interconnect, named darkNoC, that consists of multiple NoCs where each NoC is optimised at design time using multi-vt optimisation for different voltage-frequency (VF) levels. This architecture can provide up to 52% saving in NoC energy delay product (EDP) for certain benchmarks, whereas state-of-the-art DVFS scheme only saved 15% EDP. Then, the Malleable NoC architecture is proposed, which further improves the energy efficiency of darkNoC by a combination of multiple VF optimised routers and per node VF selection, and by exploiting the heterogeneity of application workload and application-to-core mapping. Next, this thesis proposes SuperNet NoC architecture, that exchanges dark silicon for optimising the energy, performance and reliability of on-chip interconnect. SuperNet consists of two parallel NoC planes that are optimised for different VF levels, and can be configured at runtime to operate in energy efficient mode, performance mode or reliability mode. Finally, a design flow for designing custom on-chip communication for application specific MPSoCs targeting streaming applications is proposed. To reduce the runtime of the framework, a heuristic with linear time complexity is introduced for exploring exponential design space, reducing framework runtime by 27x compared to a state-of-the-art heuristic

    A second update on mapping the human genetic architecture of COVID-19

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